1. Field of the Invention
The invention relates to a dual damascene process, and more particularly to a dual damascene process capable of applying ultra low-k material.
2. Description of the Prior Art
Dual damascene process is an interconnective process for connecting a metal wire and a via plug. A dual damascene structure is preferably used for connecting difference devices and wires in a semiconductor chip while using surrounding inter-metal dielectrics and inter-layer dielectrics for isolating other devices. As dual damascene process typically performs a chemical mechanical polishing (CMP) process at the last stage to planarize the surface of the chip for facilitating deposition and photo-lithography process conducted afterwards and preparation of multilevel interconnects, dual damascene structures are commonly used in fabricating semiconductor circuits.
In addition, the combination of copper dual damascene technique and low-k dielectric layer has become the best solution for fabricating metal interconnects in high integration and high-speed logic semiconductor chips as well as deep sub-micron meter semiconductor process. As copper has a substantially lower resistance (such as 30% lower than aluminum) and better electromigration resistance and low k dielectric material has the characteristics of reducing RC delay between metal wires, the utilization of low-k dielectric material and cooper dual damascene has become critically important in semiconductor fabrication.
However, as multiple resist coatings, bottom anti-reflective coating (BARC) coatings, exposures, developments, after developing inspections (ADI), etchings, and after etching inspections (AEI) are employed in conventional dual damascene processes, the cost and time required for a typical dual damascene process become even more consuming as the process progresses into sub-micron or even nanometer level. In particular, the rework performed for abnormalities found during the fabrication further degrades the quality of the inter-metal dielectric layer and results in issues such as dielectric constant k value degradation or critical dimension variation. This further causes line distortion or fragile dielectric layer by wiggling via hole or trenches, thereby affecting the yield of the metallization afterwards.
As the development of semiconductor circuitry becomes more precise and complex, how to effectively improve the yield of dual damascene process has become an important task in this industry.